The present invention relates to timing adjustment in multistage circuit systems.
Multistage circuit systems include several segments that are driven by signals. During circuit operation, a given number of segments may be driven by the signals. Ideally, the segment outputs need to be aligned with respect to time. However, with the continued increase in operating speed and desired output frequency in multistage circuits, timing related errors are the most challenging and demanding problems. These errors include phase noise on the clock signal, duty cycle distortion, and segment to segment timing mismatch.
Timing mismatch in multistage circuits, such as converters, causes frequency and data distortion. Existing schemes for fixing timing related errors are far too invasive and susceptible to noise. Some schemes require additional circuitry and control signals on a clock signal for every segment or include overly complex adjustment circuitry for every clock line. These schemes downgrade performance by providing additional coupling paths. Other schemes involve integrating varactors on each clocked line, however, they only allow fine resolution for small voltage adjustment. Moreover, because the varactor schemes utilize voltage for timing adjustment, they are more susceptible to noise.
The inventor therefore perceives a need in the art for improved fine timing adjustment in multistage circuits without the need for adding significant circuitry or control lines.